
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 14, 1999
4241V
Features
High-speed, low-power, first-in, first-out (FIFO)
memories
64 x 9 (CY7C4421V)
256 x 9 (CY7C4201V)
512 x 9 (CY7C4211V)
1K x 9 (CY7C4221V)
2K x 9 (CY7C4231V)
4K x 9 (CY7C4241V)
8K x 9 (CY7C4251V)
High-speed 66-MHz operation (15-ns read/write cycle
time)
Low power (I
CC
= 20 mA)
3.3V operation for low power consumption and easy
integration into low-voltage systems
5V tolerant inputs V
IH max
= 5V
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and Programmable Almost Empty and
Almost Full status flags
TTL compatible
Output Enable (OE) pin
Independent read and write enable pins
Center power and ground pins for reduced noise
Width expansion capability
Space saving 32-pin 7 mm x 7 mm TQFP
32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. Programmable features include Almost Full/Al-
most Empty flags. These FIFOs provide solutions for a wide
variety of data buffering needs, including high-speed data ac-
quisition, multiprocessor interfaces, and communications buff-
ering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled
in a similar manner by a Free-Running Read Clock (RCLK)
and two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock fre-
quencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data
.
Logic Block Diagram
Pin Configuration
42X1V–1
42X1V–2
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0
8
RCLK
EF
PAE
PAF
FF
Q0
8
WEN1
WCLK
RS
OE
D64 x 9
8Kx 9
WEN2/LD
REN1 REN2
PLCC
Top View
42X1V–3
D
1
D
0
RCLK
REN2
V
CC
Q
8
Q
7
Q
6
Q
5
D
8
D
7
D
6
D
5
D
4
D
3
GND
REN1
WCLK
WEN2/LD
D
2
D
8
D
7
D
6
D
5
D
4
D
3
D
2
PAF
PAE
5
6
7
8
9
10
11
12
13
1
2
3
4
5
7
8
OE
4 3 2 1
3130
32
D
1
D
0
RCLK
REN2
GND
REN1
PAF
PAE
21
22
23
24
27
26
28
29
25
14151617181920
17
18
19
20
21
22
23
24
14 15 16
9 10 11 1213
31 30
32
2928 27
25
26
WEN1
RS
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
O
V
CC
Q
8
Q
7
Q
6
Q
5
WCLK
WEN2/LD
WEN1
R
TQFP
Top View