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參數(shù)資料
| 型號： | CY7C421 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512 x 9 Asynchronous FIFO(512 x 9 位異步先進先出（FIFO）) |
| 中文描述： | 512 × 9異步FIFO（512 × 9位異步先進先出（FIFO）的） |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 483K |
| 代理商： | CY7C421 |
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *B
Page 11 of 25
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of
dual-port RAM cells), a read pointer, a write pointer, control
signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and
Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is
necessary to achieve truly asynchronous operation of the
inputs and outputs. A second benefit is that the time required
to increment the read and write pointers is much less than the
time that would be required for data propagation through the
memory, which would be the case if the memory were imple-
mented using the conventional register array architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH t
RPW
/t
WPW
before and t
RMR
after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D
0
–D
8
) t
SD
before and t
HD
after the
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs t
WEF
after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW t
WHF
after the falling edge of W following the FIFO
actually being Half Full. Therefore, the HF is active once the
Expansion Timing Diagrams
Note:
15.Expansion Out of device 1 (XO
1
) is connected to Expansion In of device 2 (XI
2
).
Switching Waveforms
(continued)
R
W
XO
1
(XI
2
)
D
0
–D
8
DATA VALID
DATA
VALID
DATA
VALID
t
XOL
t
XOH
t
HD
t
SD
t
SD
t
HD
t
XOL
t
LZR
t
A
t
DVR
t
XOH
t
A
t
DVR
t
HZR
XO
1
(XI
2
)
Q
0
–Q
8
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
t
WR
t
RR
DATA VALID
[15]
[15]
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參數(shù)描述 |
|---|---|
| CY7C4211 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C421-10JC | 制造商:Rochester Electronics LLC 功能描述:512 X 9 28 PIN .300 PARALLEL-CASCADEABLEFIFO " - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C421-10JXC | 功能描述:IC ASYNC FIFO MEM 512X9 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C421-10JXCT | 功能描述:IC ASYNC FIFO MEM 512X9 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C421-10PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 512 x 9 28-Pin PDIP |
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