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參數(shù)資料
| 型號： | CY7C4215 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512 x 18 Synchronous FIFOs(512 x 18 同步 先進先出) |
| 中文描述： | 512 × 18（512 × 18同步先進先出同步FIFO的） |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 398K |
| 代理商： | CY7C4215 |
CY7C4425/4205/4215
CY7C4225/4235/4245
6
t
PAFasynch
Clock to Programmable Almost-Full Flag
[12]
(Asynchronous mode, V
CC
/SMODE tied to V
CC
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to V
SS
)
Clock to Programmable Almost-Empty Flag
[12]
(Asynchronous mode, V
CC
/SMODE tied to V
CC
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to V
SS
)
Clock to Half-Full Flag
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-Up Time
Skew Time between Read Clock and Write
Clock for Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Pro-
grammable Almost Full Flags.
12
16
20
25
ns
t
PAFsynch
8
10
15
20
ns
t
PAEasynch
12
16
20
25
ns
t
PAEsynch
8
10
15
20
ns
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
12
7
16
10
20
15
25
20
ns
ns
ns
ns
ns
3
6.5
5
6
10
10
10
14
15
12
4.5
5
t
SKEW2
5
6
10
12
ns
t
SKEW3
10
15
18
20
ns
Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
7C42X5-10
Min.
7C42X5-15
Min.
7C42X5-25
Min.
7C42X5-35
Min.
Max.
Max.
Max.
Max.
Unit
Switching Waveforms
Notes:
12.
13. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then FF may not change state until the next WCLK edge.
PAFasynch
, t
, after program register write will not be valid until 5 ns + t
.
Write Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
DS
t
SKEW1
t
ENS
WEN
t
CLK
t
DH
t
WFF
t
WFF
t
ENH
WCLK
D
0
–D
17
FF
REN
RCLK
42X5–6
[13]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4235 | 2K x 18 Synchronous FIFOs(2K x 18 同步先進先出) |
| CY7C4425 | 64 x 18 Synchronous FIFOs(64 x 18 同步 先進先出) |
| CY7C4211 | 512 x 9 Synchronous FIFOs(512x9同步先進先出（FIFO）) |
| CY7C4201 | 256 x 9 Synchronous FIFOs(256x9同步先進先出（FIFO）) |
| CY7C4221 | 1K x 9 Synchronous FIFOs(1Kx9同步先進先出（FIFO）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4215 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4215-15AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4215-15AIT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4215-15AXI | 功能描述:先進先出 512x18 IDT Compat SYNC 先進先出 IND RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4215-15AXIT | 功能描述:先進先出 512x18 IDT Compat SYNC 先進先出 IND RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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