- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379091 > CY7C374i (Cypress Semiconductor Corp.) UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) PDF資料下載
參數(shù)資料
| 型號： | CY7C374i |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
| 中文描述： | UltraLogic 128宏單元CPLD的閃光（超邏輯的128個宏單元閃速的CPLD） |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 283K |
| 代理商： | CY7C374I |
CY7C374i
5
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................
–
65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................
–
55
°
C to +125
°
C
Supply Voltage to Ground Potential ...............
–
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State...............................................
–
0.5V to +7.0V
DC Input Voltage............................................
–
0.5V to +7.0V
DC Program Voltage .....................................................12.5V
Output Current into Outputs.........................................16 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Notes:
2.
3.
4.
5.
6.
T
is the
“
instant on
”
case temperature.
See the last page of this specification for Group A subgroup testing information.
If V
is not specified, the device can be operating in either 3.3V or 5V I/O mode; V
CC
=V
CCINT
.
I
=
–
2
mA, I
= 2 mA for SDO.
When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note
“
Understanding Bus Hold
”
for additional
information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
OUT
= 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
7.
8.
9.
Operating Range
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
V
CC
V
CCINT
5V
±
0.25V
V
CCIO
5V
±
0.25V
OR
3.3V
±
0.3V
5V
±
0.5V
OR
3.3V
±
0.3V
Industrial
40
°
C to +85
°
C
5V
±
0.5V
Military
[2]
–
55
°
C to +125
°
C
5V
±
0.5V
Electrical Characteristics
Over the Operating Range
[3, 4]
Parameter
V
OH
Description
Test Conditions
I
OH
=
–
3.2 mA (Com
’
l/Ind)
[5]
I
OH
=
–
2.0 mA (Mil)
I
OH
= 0
μ
A (Com
’
l/Ind)
[5, 6]
I
OH
=
–
50
μ
A (Com
’
l/Ind)
[5, 6]
I
OL
= 16 mA (Com
’
l/Ind)
[5]
I
OL
= 12 mA (Mil)
Guaranteed Input Logical HIGH voltage for all inputs
[7]
Guaranteed Input Logical LOW voltage for all inputs
[7]
V
I
= Internal GND, V
I
= V
CC
V
CC
= Max., V
O
= GND or V
O
= V
CC
, Output Disabled
V
CC
= Max., V
O
= 3.3V, Output Disabled
[6]
V
CC
= Max., V
OUT
= 0.5V
Min.
2.4
Typ.
Max.
Unit
V
V
V
V
V
V
V
V
μ
A
μ
A
μ
A
mA
Output HIGH Voltage
V
CC
= Min.
V
OHZ
Output HIGH Voltage
with Output Disabled
[9]
V
CC
= Max.
4.0
3.6
0.5
V
OL
Output LOW Voltage
V
CC
= Min.
V
IH
V
IL
I
IX
I
OZ
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
2.0
–
0.5
–
10
–
50
0
–
30
7.0
0.8
+10
+50
–
125
–
160
–
70
I
OS
Output Short
Circuit Current
[8, 9]
Power Supply Current
I
CC
V
CC
= Max., I
OUT
= 0 mA,
f = 1 MHz, V
IN
= GND, V
CC[10]
Com
’
l/Ind.
Com
’
l
“
L
”
–
66
Military
125
75
125
200
125
250
mA
mA
mA
μ
A
I
BHL
Input Bus Hold LOW
Sustaining Current
Input Bus Hold HIGH
Sustaining Current
Input Bus Hold LOW
Overdrive Current
Input Bus Hold HIGH
Overdrive Current
V
CC
= Min., V
IL
= 0.8V
+75
I
BHH
V
CC
= Min., V
IH
= 2.0V
–
75
μ
A
I
BHLO
V
CC
= Max.
+500
μ
A
I
BHHO
V
CC
= Max.
–
500
μ
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C374 | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
| CY7C375i | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128-宏單元閃速CPLD) |
| CY7C375 | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
| CY7C402 | 64 x 5 Cascadable FIFO(64 x 5位級聯(lián)型先進先出（FIFO）) |
| CY7C401 | 64 x 4 Cascadable FIFO(64 x 4 位級聯(lián)型先進先出（FIFO）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C374I100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C374I-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C374I-100JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 3.2K Gates 128 Macro Cells 5V 84-Pin PLCC |
| CY7C374I-125AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C374I-125JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。