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參數(shù)資料
| 型號： | CY7C374I-66JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | UltraLogic 128-Macrocell Flash CPLD |
| 中文描述： | FLASH PLD, 20 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 274K |
| 代理商： | CY7C374I-66JI |
CY7C374i
7
Switching Characteristics
Over the Operating Range
[14]
7C374i–125
Min.
7C374i–100
Min.
7C374i–83
Min.
7C374i–66
7C374iL–66
Min.
Parameter
Combinatorial Mode Parameters
t
PD
t
PDL
Input to Output Through Transparent Input or
Output Latch
[1]
t
PDLL
Input to Output Through Transparent Input
and Output Latches
[1]
t
EA
t
ER
Input to Output Disable
Input Registered/Latched Mode Parameters
t
WL
t
WH
t
IS
Input Register or Latch Set-Up Time
t
IH
Input Register or Latch Hold Time
t
ICO
Input Register Clock or Latch Enable to Com-
binatorial Output
[1]
t
ICOL
Input Register Clock or Latch Enable to Out-
put Through Transparent Output Latch
[1]
Output Registered/Latched Mode Parameters
t
CO
t
S
Set-Up Time from Input to Clock or Latch En-
able
t
H
Register or Latch Data Hold Time
t
CO2
Output Clock or Latch Enable to Output Delay
(Through Memory Array)
[1]
t
SCS
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
t
SL
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch En-
able
t
HL
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
f
MAX1
Maximum Frequency with Internal Feedback
(Least of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[9]
f
MAX2
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
WL
+
t
WH
), 1/(t
S
+ t
H
), or 1/t
CO
)
f
MAX3
Maximum Frequency with External Feedback
(Lesser of 1/(t
CO
+ t
S
) and 1/(t
WL
+ t
WH
))
t
OH
–t
IH
37x
Input Register Hold Time for 7C37x
[9, 15]
Pipelined Mode Parameters
t
ICS
Input Register Clock to Output Register Clock
f
MAX4
Maximum Frequency in Pipelined Mode
(Least of 1/(t
CO
+ t
IS
), 1/t
ICS
, 1/(t
WL
+ t
WH
),
1/(t
IS
+ t
IH
), or 1/t
SCS
)
Notes:
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
Description
Max.
Max.
Max.
Max.
Unit
Input to Combinatorial Output
[1]
10
13
12
15
15
18
20
22
ns
ns
15
16
19
24
ns
Input to Output Enable
[1]
14
14
16
16
19
19
24
24
ns
ns
Clock or Latch Enable Input LOW Time
[9]
Clock or Latch Enable Input HIGH Time
[9]
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
14
16
19
24
16
18
21
26
ns
Clock or Latch Enable to Output
[1]
6.5
7
8
10
ns
ns
5.5
6
8
10
0
0
0
0
ns
ns
14
16
19
24
8
10
12
15
ns
10
12
15
20
ns
0
0
0
0
ns
125
100
83
66
MHz
158.3
143
125
100
MHz
83.3
76.9
67.5
50
MHz
Output Data Stable from Output Clock Minus
0
0
0
0
ns
8
10
100
12
83.3
15
66.6
ns
MHz
125
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C374I-66YMB | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374i | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
| CY7C374 | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
| CY7C375i | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128-宏單元閃速CPLD) |
| CY7C375 | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C374I83AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C374I-83AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 3.2K Gates 128 Macro Cells 5V 100-Pin TQFP |
| CY7C374I-83JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 3.2K Gates 128 Macro Cells CMOS Technology 5V 84-Pin PLCC |
| CY7C374U66JC | 制造商:CYPRESS 功能描述:New |
| CY7C3751-66UMB | 制造商: 功能描述: 制造商:undefined 功能描述: |
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