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參數(shù)資料
| 型號： | CY7C2566KV18-450BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 831K |
| 代理商： | CY7C2566KV18-450BZI |
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PRELIMINARY
CY7C2566KV18, CY7C2577KV18
CY7C2568KV18, CY7C2570KV18
Document Number: 001-15889 Rev. *D
Page 10 of 28
Table 3. Truth Table
The truth table for the CY7C2566KV18, CY7C2577KV18, CY7C2568KV18, and CY7C2570KV18 follow. [4, 5, 6, 7, 8, 9]
Operation
K
LD
R/W
DQ
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H
L
D(A) at K(t + 1)
↑
D(A+1) at K(t + 1)
↑
Read Cycle: (2.5 cycle Latency)
Load address; wait two and half cycles;
read data on consecutive K and K rising edges.
L-H
L
H
Q(A) at K(t + 2)
↑
Q(A+1) at K(t + 3)
↑
NOP: No Operation
L-H
H
X
High-Z
Standby: Clock Stopped
Stopped
X
Previous State
Table 4. Write Cycle Descriptions
The write cycle description table for CY7C2566KV18 and CY7C2568KV18 follows. [4, 10]
BWS0/
NWS0
BWS1/
NWS1
K
Comments
L
L–H
–
During the data portion of a write sequence
:
CY7C2566KV18
both nibbles (D[7:0]) are written into the device.
CY7C2568KV18
both bytes (D[17:0]) are written into the device.
L
–
L-H During the data portion of a write sequence
:
CY7C2566KV18
both nibbles (D[7:0]) are written into the device.
CY7C2568KV18
both bytes (D[17:0]) are written into the device.
L
H
L–H
–
During the data portion of a write sequence
:
CY7C2566KV18
only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C2568KV18
only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
–
L–H During the data portion of a write sequence
:
CY7C2566KV18
only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C2568KV18
only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
–
During the data portion of a write sequence
:
CY7C2566KV18
only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C2568KV18
only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
–
L–H During the data portion of a write sequence
:
CY7C2566KV18
only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C2568KV18
only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L–H
–
No data is written into the devices during this portion of a write operation.
H
–
L–H No data is written into the devices during this portion of a write operation.
Notes
4. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
5. Device powers up deselected with the outputs in a tri-state condition.
6. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
7. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
9. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
10. Is based on a write cycle that was initiated in accordance with Table 4. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write
cycle, as long as the setup and hold requirements are achieved.
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