參數(shù)資料
型號: CY7C2566KV18-450BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 8M X 8 DDR SRAM, 0.37 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 13/28頁
文件大?。?/td> 831K
代理商: CY7C2566KV18-450BZI
PRELIMINARY
CY7C2566KV18, CY7C2577KV18
CY7C2568KV18, CY7C2570KV18
Document Number: 001-15889 Rev. *D
Page 20 of 28
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.3V
DC Input Voltage [13].............................. –0.5V to VDD + 0.3V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature (TA)
VDD [17]
VDDQ [17]
Commercial
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
Industrial
–40°C to +85°C
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [14]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
IO Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 18
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 19
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = 0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.15
V
VIL
Input LOW Voltage
–0.15
VREF – 0.1
V
IX
Input Leakage Current
GND
≤ VI ≤ VDDQ
2
μA
IOZ
Output Leakage Current
GND
≤ VI ≤ VDDQ, Output Disabled
2
μA
VREF
Input Reference Voltage [20] Typical Value = 0.75V
0.68
0.75
0.95
V
IDD [21]
VDD Operating Supply
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
550 MHz
(x8)
740
mA
(x9)
740
(x18)
760
(x36)
970
500 MHz
(x8)
690
mA
(x9)
690
(x18)
700
(x36)
890
450 MHz
(x8)
630
mA
(x9)
630
(x18)
650
(x36)
820
400 MHz
(x8)
580
mA
(x9)
580
(x18)
590
(x36)
750
Notes
17. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
18. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
19. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
20. VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.
21. The operation current is calculated with 50% read cycle and 50% write cycle.
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