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參數(shù)資料
| 型號(hào)： | CY7C196 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 4 Static RAM(64K x 4靜態(tài) RAM) |
| 中文描述： | 64K的× 4靜態(tài)存儲(chǔ)器（64K的靜態(tài)內(nèi)存× 4） |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大小： | 203K |
| 代理商： | CY7C196 |
CY7C194
CY7C195
CY7C196
4
:
Switching Characteristics
Over the Operating Range
[7]
7C194-12
7C195-12
7C196-12
Min.
7C194-15
7C195-15
7C196-15
Min.
7C194-20
7C195-20
7C196-20
Min.
7C194-25
7C195-25
7C196-25
Min.
7C194-35
7C195-35
7C196-35
Min.
7C194-45
7C196-45
Min.
Parameter
READ CYCLE
t
RC
t
AA
Description
Max.
Max.
Max.
Max.
Max.
Max.
Unit
Read Cycle Time
12
15
20
25
35
45
ns
Address to Data
Valid
12
15
20
25
35
45
ns
t
OHA
Output Hold from
Address Change
3
3
3
3
3
3
ns
t
ACE1
,
t
ACE2
t
DOE
CE LOW to
Data Valid
12
15
20
25
35
45
ns
OE LOW to
Data Valid
7C195,
7C196
5
7
9
10
16
16
ns
t
LZOE
OE LOW to
Low Z
7C195,
7C196
0
0
0
3
3
3
ns
t
HZOE
OE HIGH to
High Z
[8]
7C195,
7C196
5
7
9
11
15
15
ns
t
LZCE1
,
t
LZCE2
t
HZCE1
,
t
HZCE2
t
PU
CE LOW to
Low Z
[8]
3
3
3
3
3
3
ns
CE HIGH to
High Z
[8,8]
5
7
9
11
15
15
ns
CE LOW to
Power-Up
0
0
0
0
0
0
ns
t
PD
CE HIGH to
Power-Down
12
15
20
25
35
45
ns
WRITE CYCLE
[10]
t
WC
t
SCE
t
AW
Write Cycle Time
12
15
20
25
35
45
ns
CE LOW to Write End
9
10
15
18
22
22
ns
Address Set-Up to
Write End
9
10
15
20
25
35
ns
t
HA
Address Hold from
Write End
0
0
0
0
0
0
ns
t
SA
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
t
PWE
t
SD
WE Pulse Width
8
9
15
18
22
22
ns
Data Set-Up to
Write End
8
9
10
10
15
15
ns
t
HD
Data Hold from
Write End
0
0
0
0
0
0
ns
t
LZWE
WE HIGH to
Low Z
[8]
3
3
3
3
3
3
ns
t
HZWE
WE LOW to
High Z
[8, 9]
7
7
10
0
13
0
15
0
20
ns
Notes:
7.
Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I
/I
and 30-pF load capacitance.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
At any given temperature and voltage condition, t
is less than t
and t
is less than t
for any given device.
9.
LOW, CE
LOW, and WE LOW. All signals must be LOW to initiate a write and any signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
8.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C196-20VC | 制造商:Cypress Semiconductor 功能描述: |
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| CY7C19635PC | 制造商:CYPRESS 功能描述:* |
| CY7C19645PC | 制造商:CYPRESS 功能描述:* |
| CY7C197 WAF | 制造商:Cypress Semiconductor 功能描述: |
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