參數(shù)資料
型號(hào)： CY7C195
廠商： Cypress Semiconductor Corp.
英文描述： 64K x 4 Static RAM(64K x 4靜態(tài) RAM)
中文描述： 64K的× 4靜態(tài)存儲(chǔ)器（64K的靜態(tài)內(nèi)存× 4）
文件頁(yè)數(shù)： 5/11頁(yè)
文件大?。?/td> 203K
代理商： CY7C195
CY7C194
CY7C195
CY7C196
5
Switching Waveforms
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected: CE
= V
, CE
= V
IL
(7C196), and OE = V
IL
(7C195 and 7C196).
13. Address valid prior to or coincident with CE
and CE
transition LOW.
14. Data I/O will be high impedance if OE = V
(7C195 and 7C196).
15. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Read Cycle No. 1
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
C194-8
[11, 12]
[11, 13]
Read Cycle No. 2
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
C194-6
ICC
ISB
IMPEDANCE
CE
1
, CE
2
OE
(7C195 and
7C196)
DATA OUT
V
SUPPLY
CURRENT
C194-7
Write Cycle No. 1 (CE Controlled)
t
WC
DATA VALID
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
[10, 14, 15]
WE
DATA I/O
ADDRESS
CE
1
CE
2
(7C196)
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