- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379090 > CY7C194 (Cypress Semiconductor Corp.) 64K x 4 Static RAM(64K x 4靜態(tài) RAM) PDF資料下載
參數(shù)資料
| 型號： | CY7C194 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 4 Static RAM(64K x 4靜態(tài) RAM) |
| 中文描述： | 64K的× 4靜態(tài)存儲器（64K的靜態(tài)內(nèi)存× 4） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 203K |
| 代理商： | CY7C194 |
64K x 4 Static RAM
CY7C194
CY7C195
CY7C196
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 27, 1999
Features
High speed
—12 ns
Output enable (OE) feature (7C195 and 7C196)
CMOS for optimum speed/power
Low active power
—880 mW
Low standby power
—220 mW
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY7C194, CY7C195, and CY7C196 are high-perfor-
mance CMOS static RAMs organized as 65,536 by 4 bits.
Easy memory expansion is provided by active LOW Chip En-
able(s) (CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) and three-state drivers. They have an automatic
power-down feature, reducing the power consumption by 75%
when deselected.
Writing to the device is accomplished when the Chip Enable(s)
(CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) and Write Enable (WE) inputs are both LOW. Data
on the four input pins (I/O
0
through I/O
3
) is written into the
memory location, specified on the address pins (A
0
through
A
15
).
Reading the device is accomplished by taking the Chip En-
able(s) (CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) LOW, while Write Enable (WE) remains HIGH. Un-
der these conditions the contents of the memory location
specified on the address pins will appear on the four data I/O
pins.
A die coat is used to ensure alpha immunity.
CE
GND
Logic Block Diagram
Pin Configurations
DIP/SOJ
1024 x 64 x 4
ARRAY
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
0
A
1
A
1
A
1
A
1
A
1
COLUMN
DECODER
R
S
POWER
DOWN
WE
(OE)
(7C195 and
7C196 ONLY)
I/O
3
2
(7C196 only)
CE
1
I/O
2
I/O
1
I/O
0
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
20
19
18
17
21
24
23
22
Top View
7C194
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
WE
V
CC
I/O
3
I/O
2
I/O
1
I/O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
7C195
7C196
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
WE
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
3
I/O
2
I/O
1
I/O
0
CE
1
OE
NC
CE
(7C196)
INPUT BUFFER
C194-1
C194-2
C194-3
NC
(7C195)
Selection Guide
7C194-12
7C195-12
7C196-12
12
155
30
7C194-15
7C195-15
7C196-15
15
145
30
7C194-20
7C195-20
7C196-20
20
135
30
7C194-25
7C195-25
7C196-25
25
115
30
7C194-35
7C195-35
7C196-35
35
115
30
7C194-45
7C196-45
45
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C195 | 64K x 4 Static RAM(64K x 4靜態(tài) RAM) |
| CY7C196 | 64K x 4 Static RAM(64K x 4靜態(tài) RAM) |
| CY7C1992BV18 | 18-Mbit DDR-II SIO SRAM 2-Word(2字Burst結(jié)構(gòu),18-Mbit DDR-II SIO SRAM) |
| CY7C199 | 32K x 8 Static RAM(32K x 8靜態(tài) RAM) |
| CY7C271A-35PC | 32K x 8 Power Switched and Reprogrammable PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C194-20VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 64K x 4-Bit 20ns 24-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:256K (64K X 4)- FAST ASYNCH SRAM - Bulk |
| CY7C194-20VCT | 制造商:Rochester Electronics LLC 功能描述:256K (64K X 4)- FAST ASYNCH SRAM - Bulk |
| CY7C19425PC | 制造商:CYPRESS 功能描述:New |
| CY7C194-25PC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 64K x 4-Bit 25ns 24-Pin PDIP |
| CY7C194-25SC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。