參數(shù)資料
型號(hào)： CY7C1527V18-300BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述： 8M X 9 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 9/28頁(yè)
文件大小： 457K
代理商： CY7C1527V18-300BZXC
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 9 of 28
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
SS
to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
and 350
,
with
V
DDQ
= 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the DDR-II. In the single clock mode, CQ is generated with
respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.
Notes:
2. The above application shows two DDR-II used.
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
4. Device will power-up deselected and the outputs in a tri-state condition.
5. On CY7C1518V18 and CY7C1520V18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1516V18, “A1” represents A +‘0’ and A2 represents A +‘1.’
6. “t” represents the cycle at which a Read/Write operation is started. t+1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Application Example
[2]
Truth Table
[3, 4, 5, 6, 7, 8]
Operation
K
LD
L
R/W
L
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle; read data on
consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
L-H
D(A1) at K(t + 1)
↑
D(A2) at K(t + 1)
↑
L-H
L
H
Q(A1) at C(t + 1)
↑
Q(A2) at C(t + 2)
↑
L-H
H
X
X
X
High-Z
Previous State
High-Z
Previous State
Stopped
LD#
Vterm = 0.75V
Vterm = 0.75V
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
LD#
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
BUS
MASTER
(CPU
or
ASIC)
SRAM#1
SRAM#2
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
R = 50
ohms
R = 250
ohms
R
= 250ohms
Burst Address Table
(CY7C1518V18, CY7C1520V18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
[+] Feedback
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