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參數(shù)資料
| 型號： | CY7C185A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8K x 8 Static RAM(8Kx8靜態(tài) RAM) |
| 中文描述： | 8K的× 8靜態(tài)RAM（8Kx8靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 142K |
| 代理商： | CY7C185A |
8K x 8 Static RAM
CY7C185A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 4, 1999
Features
High speed
—20 ns
CMOS for optimum speed/power
Low active power
—743 mW
Low standby Power
—220 mW
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
Functional Description
The CY7C185A is a high-performance CMOS static RAM or-
ganized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE
1
), an active HIGH
Chip Enable (CE
2
), an active LOW Output Enable (OE), and
three-state drivers. The device has an automatic power-down
feature (CE
1
), reducing the power consumption by over 70%
when deselected. The CY7C185A is in the standard
300-mil-wide DIP package and leadless chip carrier.
Writing to the device is accomplished when the Chip Enable
one (CE
1
) and Write Enable (WE) inputs are both LOW, and
the Chip Enable two (CE
2
) input is HIGH.
Data on the eight I/O pins (I/O
0
through I/O
7
) is written into the
memory location specified on the address pins (A
0
through
A
12
).
Reading the device is accomplished by taking Chip Enable
one (CE
1
) and Output Enable (OE) LOW, while taking Write
Enable (WE) and Chip Enable two (CE
2
) HIGH. Under these
conditions, the contents of the memory location specified on
the address pins will appear on the I/O pins.
The I/O pins remain in a high-impedance state when Chip En-
able one (CE
1
) or Output Enable (OE) is HIGH, or Write En-
able (WE) or Chip Enable two (CE
2
) is LOW.
A die coat is used to ensure alpha immunity.
28
Logic Block Diagram
Pin Configurations
C185A–1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
0
A
1
A
9
A
1
A
1
I/O
0
4
5
6
7
8
9
10
11
12
3 2 1
27
1314151617
26
25
24
23
22
21
20
19
18
A6
VC
NC
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
G
Top View
LCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
W
I
I
I
I
A
A
8K x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
R
S
POWER
DOWN
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
CE
2
WE
OE
Top View
DIP
C185A–2
C185A–3
Selection Guide
[1]
7C185A–20
20
135
40/20
7C185A–25
25
125
40/20
7C185A–35
35
125
30/20
7C185A–45
45
125
30/20
Maximum Access Time (ns)
Maximum Operating Current (mA) Military
Maximum Standby Current (mA)
Military
Note:
1.
For commercial specifications, see the CY7C185 data sheet.
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