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參數(shù)資料
| 型號(hào)： | CY7C1522AV18-250BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 1133K |
| 代理商： | CY7C1522AV18-250BZI |
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PRELIMINARY
CY7C1522AV18
CY7C1529AV18
CY7C1523AV18
CY7C1524AV18
Document #: 001-06981 Rev. *B
Page 22 of 28
Switching Characteristics
Over the Operating Range
[22, 23]
Cypress
Parameter
t
POWER
Consortium
Parameter
Description
300 MHz
Min. Max.
1
278 MHz
Min. Max. Min. Max. Min. Max. Min.
1
1
250 MHz
200 MHz
167 MHz
Unit
ms
Max.
V
DD
(Typical) to the first
Access
[24]
K Clock and C Clock
Cycle Time
Input Clock (K/K and
C/C) HIGH
Input Clock (K/K and
C/C) LOW
K Clock Rise to K Clock
Rise and C to C Rise
(rising edge to rising
edge)
K/K Clock Rise to C/C
Clock Rise (rising edge to
rising edge)
1
1
t
CYC
t
KHKH
3.30
5.25
3.60
5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
t
KH
t
KHKL
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KL
t
KLKH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KHKH
t
KHKH
1.49
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHCH
0
1.45
0
1.55
0
1.8
0
2.2
0
2.7
ns
Set-up Times
t
SA
t
AVKH
Address Set-up to K
Clock Rise
Control Set-up to K Clock
Rise (LD, R/W)
Double Data Rate
Control Set-up to Clock
(K/K) Rise (BWS
0
,
BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Set-up to Clock
(K/K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SC
t
IVKH
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SCDDR
t
IVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
SD[26]
t
DVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K
Clock Rise
Control Hold after K
Clock Rise (LD, R/W)
Double Data Rate
Control Hold after Clock
(K/K) Rise (BWS
0
,
BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Hold after Clock
(K/K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HC
t
KHIX
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HCDDR
t
KHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise
(or K/K in single clock
mode) to Data Valid
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
Notes:
22.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
23.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250
, V
DDQ
= 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified I
/I
and load capacitance shown in (a) of AC Test Loads.
24.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
25.For D0 data signal on CY7C1529AV18 device, t
SD
is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.
[+] Feedback
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| CY7C1522AV18-250BZXC | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
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