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參數(shù)資料
| 型號： | CY7C1520AV18-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 36 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 1133K |
| 代理商： | CY7C1520AV18-167BZC |
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PRELIMINARY
CY7C1516AV18
CY7C1527AV18
CY7C1518AV18
CY7C1520AV18
Document #: 001-06982 Rev. *B
Page 22 of 28
Switching Characteristics
Over the Operating Range
[22, 23]
Cypress
Parameter
t
POWER
Consortium
Parameter
Description
300 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
–
1
–
1
278 MHz
250 MHz
200 MHz
167 MHz
Unit
ms
V
DD
(Typical) to the first
Access
[24]
K Clock and C Clock Cycle
Time
–
1
–
1
–
t
CYC
t
KHKH
3.30 5.25
3.60
5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
t
KH
t
KHKL
Input Clock (K/K and C/C)
HIGH
Input Clock (K/K and C/C)
LOW
K Clock Rise to K Clock Rise
and C to C Rise (rising edge
to rising edge)
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KL
t
KLKH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KHKH
t
KHKH
1.49
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHCH
0
1.45
0
1.55
0
1.8
0
2.2
0
2.7
ns
Set-up Times
t
SA
t
AVKH
Address Set-up to K Clock
Rise
Control Set-up to K Clock
Rise (LD, R/W)
Double Data Rate Control
Set-up to Clock (K, K) Rise
(BWS
0
, BWS
1
, BWS
2
,
BWS
3
)
D
[X:0]
Set-up to Clock
(K and K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SC
t
IVKH
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SCDDR
t
IVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
SD[26]
t
DVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock
Rise
Control Hold after K Clock
Rise (RPS, WPS)
Double Data Rate Control
Hold after Clock (K and K)
Rise (BWS
0
, BWS
1
, BWS
2
,
BWS
3
)
D
[X:0]
Hold after Clock
(K and K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HC
t
KHIX
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HCDDR
t
KHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in single
clock mode) to Data Valid
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
t
CCQO
t
CHCQV
C/C Clock Rise to Echo
Clock Valid
Echo Clock Hold after C/C
Clock Rise
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
CQOH
t
CHCQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
Notes:
23.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
24.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
25.For DQ0 data signal on CY7C1527AV18 device, t
SD
is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1520AV18-167BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520AV18-167BZXC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520AV18-167BZXI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520AV18-200BZC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520AV18-200BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1520AV18-200BZC | 功能描述:靜態(tài)隨機存取存儲器 2M x 36 1.8V DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1520AV18-200BZCT | 功能描述:IC SRAM 72MBIT 200MHZ 165TFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| CY7C1520AV18-200BZI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1520AV18-200BZXI | 功能描述:靜態(tài)隨機存取存儲器 2Mx36 1.8V DDR-II (2-Word Burst) RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1520AV18-250BZC | 功能描述:靜態(tài)隨機存取存儲器 2M x 36 1.8V DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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