參數(shù)資料
型號(hào)： CY7C1518V18-300BZC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 72-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述： 4M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 457K
代理商： CY7C1518V18-300BZC
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 19 of 28
Power-Up Sequence in DDR-II SRAM
[14, 15]
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
— Apply V
DD
before V
DDQ
— Apply V
DDQ
before V
REF
or at the same time as V
REF
After the power and clock (K, K, C, C) are stable take DOFF
HIGH
The additional 1024 cycles of clocks are required for the
DLL to lock.
Power-up Waveforms
DLL Constraints
DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
t
KC Var
.
The DLL will function at frequencies down to 80 MHz.
If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
.
Notes:
14.It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
15.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
> 1024 Stable clock
Start Normal
Operation
DOFF
Stabl
e
(< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
K
K
DDQ
V
DD
V
/
DDQ
DD
V
V
/
Clock Start
(
Clock Starts after DD
)
V
/
~
~
~
~
Unstable Clock
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1518V18-300BZI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518V18-300BZXC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518V18-300BZXI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-167BZC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-167BZI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1518XC 制造商:Cypress Semiconductor 功能描述:
CY7C1518YC 制造商:Cypress Semiconductor 功能描述:
CY7C1518ZC 制造商:Cypress Semiconductor 功能描述:
CY7C1520AV18-200BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 36 1.8V DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1520AV18-200BZCT 功能描述:IC SRAM 72MBIT 200MHZ 165TFBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤(pán) 其它名稱(chēng):71P71804S200BQ
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