參數(shù)資料
型號: CY7C1475V25-133BGXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture
中文描述: 1M X 72 ZBT SRAM, 6.5 ns, PBGA209
封裝: 14 X 22 MM, 1.76 MM HEIGHT, LEAD FREE, FBGA-209
文件頁數(shù): 25/32頁
文件大?。?/td> 928K
代理商: CY7C1475V25-133BGXI
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *I
Page 25 of 32
Figure 2
shows NOP, STALL and DESELECT Cycles waveform.
[19, 20, 22]
Figure 2. NOP, STALL and DESELECT Cycles
Switching Waveforms
(continued)
READ
Q(A3)
4
5
6
7
8
9
10
A3
A4
A5
D(A4)
1
2
3
CLK
CE
WE
CEN
BW
[A:D]
ADV/LD
ADDRESS
DQ
COMMAND
WRITE
D(A4)
STALL
WRITE
D(A1)
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tCHZ
A1
A2
Q(A2)
D(A1)
Q(A3)
tDOH
Q(A5)
Note
22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
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CY7C1475V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
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