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參數(shù)資料
| 型號： | CY7C1472V33-200BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| 中文描述： | 4M X 18 ZBT SRAM, 3 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 378K |
| 代理商： | CY7C1472V33-200BZXC |
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PRELIMINARY
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *E
Page 15 of 28
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
[12]
Architecture/Memory
Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
CY7C1470V33
(2M x 36)
000
01011
001000
CY7C1472V33
(4M x 18)
000
01011
001000
CY7C1474V33
(1M x 72)
000
01011
001000
Description
Describes the version number
Reserved for internal use
Defines memory type and archi-
tecture
Defines width and density
Allows unique identification of
SRAM vendor
Indicates the presence of an ID
register
100100
00000110100
010100
00000110100
110100
00000110100
1
1
1
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
71
-
Bit Size (x18)
3
1
32
52
-
Bit Size (x72)
3
1
32
-
110
Instruction
Bypass
ID
Boundary Scan Order-165FBGA
Boundary Scan Order- 209BGA
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
101
Note:
12.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1472V33-250AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1472V33-250BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1472V33-250BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1474V33 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1474V33-167BGC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1472V33-250AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 72MBIT 4MX18 3NS 100TQFP - Bulk |
| CY7C1472XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C147-35KMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1473BV33-133AXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 3.3v 133MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1474BV25-167BGC | 功能描述:靜態(tài)隨機存取存儲器 1Mx72, 2.5V NoBL PL RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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