參數(shù)資料
型號: CY7C1471V33-100BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述: 2M X 36 ZBT SRAM, 8.5 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
文件頁數(shù): 15/29頁
文件大?。?/td> 375K
代理商: CY7C1471V33-100BZC
PRELIMINARY
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *E
Page 15 of 29
3.3V TAP AC Test Conditions
Input pulse levels................................................ V
SS
to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50
50
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 3.3V ±0.165V unless otherwise noted)
[12]
Parameter
Description
V
OH1
Output HIGH Voltage
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –4.0 mA, V
DDQ
= 3.3V
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA
V
OH2
Output HIGH Voltage
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100 μA
0.4
0.4
0.2
0.2
V
OL2
Output LOW Voltage
V
IH
Input HIGH Voltage
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
[13]
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
CY7C1471V33
(2Mx36)
000
01011
001001
100100
00000110100
CY7C1473V33
(4Mx18)
000
01011
001001
010100
00000110100
CY7C1475V33
(1Mx72)
000
01011
001001
110100
00000110100
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM
vendor
Indicates the presence of an ID register
ID Register Presence Indicator (0)
1
1
1
Notes:
12.All voltages referenced to V
(GND).
13.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
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CY7C1471V33-117AXC 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx36 3.3V NoBL FT 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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