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參數(shù)資料
| 型號(hào)： | CY7C1442AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線同步靜態(tài)存儲(chǔ)器（36字節(jié)（100萬(wàn)x 36/2M x 18/512K × 72）管道式同步靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 20/31頁(yè) |
| 文件大小： | 531K |
| 代理商： | CY7C1442AV33 |
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E
Page 20 of 31
Switching Characteristics
Over the Operating Range
[24, 25]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Description
–250
–200
–167
Unit
ms
Min.
1
Max
Min.
1
Max.
Min.
1
Max
V
DD
(Typical) to the first Access
[20]
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
1.5
1.5
5
6
ns
ns
ns
2.0
2.0
2.4
2.4
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[21, 22, 23]
Clock to High-Z
[21, 22, 23]
OE LOW to Output Valid
OE LOW to Output Low-Z
[21, 22, 23]
OE HIGH to Output High-Z
[21, 22, 23]
2.6
3.2
3.4
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
1.5
1.3
1.5
1.5
2.6
2.6
3.0
3.0
3.4
3.4
0
0
0
2.6
3.0
3.4
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
X
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
20.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
21.t
, t
,t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
22.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
23.This parameter is sampled and not 100% tested.
24.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
25.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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