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| 型號(hào)： | CY7C1411AV18-278BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| 中文描述： | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 22/28頁(yè) |
| 文件大?。?/td> | 1143K |
| 代理商： | CY7C1411AV18-278BZC |
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CY7C1411AV18
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
Document Number: 38-05614 Rev. *C
Page 22 of 28
Switching Characteristics
Over the Operating Range
[24, 25]
Cypress
Parameter
t
POWER
Consortium
Parameter
Description
300 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
1
1
278 MHz
250 MHz
200 MHz
167 MHz
Unit
ms
V
DD
(Typical) to the First
Access
[29]
1
1
t
CYC
t
KHKH
K Clock and C Clock Cycle
Time
Input Clock (K/K; C/C)
HIGH
Input Clock (K/K; C/C)
LOW
K Clock Rise to K Clock
Rise and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C
Clock Rise (rising edge to
rising edge)
3.30
5.25 3.60
5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
t
KH
t
KHKL
1.32
–
1.4
–
1.6
–
2.0
2.4
–
ns
t
KL
t
KLKH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KHKH
t
KHKH
1.49
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHCH
0.0
1.45
0.0
1.55
0.0
1.8
0.0
2.2
0.0
2.7
ns
Set-up Times
t
SA
t
AVKH
Address Set-up to K Clock
Rise
Control Set-up to K Clock
Rise (RPS, WPS)
Double Data Rate Control
Set-up to Clock (K, K) Rise
(BWS
0
, BWS
1,
BWS
2
,
BWS
3
)
D
[X:0]
Set-up to Clock (K/K)
Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SC
t
IVKH
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SCDDR
t
IVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
SD[27]
t
DVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock
Rise
Control Hold after K Clock
Rise (RPS, WPS)
Double Data Rate Control
Hold after Clock (K, K) Rise
(BWS
0
, BWS
1,
BWS
2
,
BWS
3
)
D
[X:0]
Hold after Clock
(K/K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HC
t
KHIX
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HCDDR
t
KHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
0.45
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
Notes:
25.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
26.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a Read or Write operation
can be initiated.
27.For D2 data signal on CY7C1426AV18 device, t
is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.
28.t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
29.At any given voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
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