參數(shù)資料
型號(hào)： CY7C1381D-133BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
中文描述： 512K X 36 CACHE SRAM, 6.5 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
文件頁(yè)數(shù)： 21/29頁(yè)
文件大?。?/td> 477K
代理商： CY7C1381D-133BGC
PRELIMINARY
CY7C1381D
CY7C1383D
Document #: 38-05544 Rev. *A
Page 21 of 29
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
WEH
t
ADVH
t
DH
t
CEH
Notes:
18.Tested initially and after any design or process change that may affect these parameters.
19.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
( minimum) initially, before a read or write operation
can be initiated.
20.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
[A:D]
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADSP, ADSC Hold After CLK Rise
GW,BWE, BW
[A:D]
Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
Switching Characteristics
Over the Operating Range (continued)
[20, 21]
Parameter
Description
133 MHz
Min.
100 MHz
Min.
Unit
Max.
Max.
相關(guān)PDF資料
PDF描述
CY7C1381D-133BGXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-133BZC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-133BZXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D-100AXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1381D-133BGXC 功能描述:IC SRAM 18MBIT 133MHZ 165LFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1381D-133BZI 制造商:Cypress Semiconductor 功能描述:
CY7C1381DV25-133AXC 制造商:Cypress Semiconductor 功能描述:
CY7C1381F-133BGC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1381F-133BGCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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