- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379067 > CY7C1372C (Cypress Semiconductor Corp.) 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1372C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| 中文描述： | 為512k × 36/1M × 18流水線的SRAM架構(gòu)的總線延遲 |
| 文件頁數(shù)： | 20/27頁 |
| 文件大?。?/td> | 704K |
| 代理商： | CY7C1372C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 20 of 27
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
CEN Set-up Before CLK Rise
WE, BW
x
Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
Address Hold After CLK Rise
Data Input Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
CEN Hold After CLK Rise
WE, BW
x
Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
Switching Characteristics
Over the Operating Range
[ 21, 22]
(continued)
Parameter
Description
-250
-225
-200
-167
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Switching Waveforms
Read/Write/Timing
[23,24,25]
Notes:
23.For this waveform ZZ is tied low.
24.When CE is LOW, CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH,CE
is HIGH or CE
is LOW or CE
is HIGH.
25.Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW
x
ADV/LD
t
AH
t
AS
ADDRESS
A1
A2
A3
A4
A5
A6
A7
t
DH
t
DS
Data
In-Out (DQ)
t
CLZ
D(A1)
D(A2)
D(A5)
Q(A4)
Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE
UNDEFINED
Q(A6)
Q(A4+1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1372C-167AC | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1372C-167AI | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1372C-250BZI | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1370D-225BGC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1370D-250AXI | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1372C-133BZC | 制造商:Cypress Semiconductor 功能描述:16MB (1MX18) 3.3V NOBL-PIPE SRAM - Bulk |
| CY7C1372C167AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372C-167AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP |
| CY7C1372C-167AI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP |
| CY7C1372C-167AIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。