參數(shù)資料
型號: CY7C1372C
廠商: Cypress Semiconductor Corp.
英文描述: 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
中文描述: 為512k × 36/1M × 18流水線的SRAM架構(gòu)的總線延遲
文件頁數(shù): 2/27頁
文件大小: 704K
代理商: CY7C1372C
CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 2 of 27
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
Sleep
Logic Block Diagram-CY7C1372C (1M x 18)
Selection Guide
CY7C1370C-250
CY7C1372C-250
2.6
350
70
CY7C1370C-225
CY7C1372C-225
2.8
325
70
CY7C1370C-200
CY7C1372C-200
3.0
300
70
CY7C1370C-167
CY7C1372C-167
3.4
275
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
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CY7C1372C-167AC 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
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參數(shù)描述
CY7C1372C-133BZC 制造商:Cypress Semiconductor 功能描述:16MB (1MX18) 3.3V NOBL-PIPE SRAM - Bulk
CY7C1372C167AC 制造商:Cypress Semiconductor 功能描述:
CY7C1372C-167AC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP
CY7C1372C-167AI 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP
CY7C1372C-167AIT 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP T/R