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參數(shù)資料
| 型號： | CY7C1372C-167AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| 中文描述： | 1M X 18 ZBT SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 9/27頁 |
| 文件大小： | 704K |
| 代理商： | CY7C1372C-167AI |
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CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 9 of 27
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SNOOZE MODE
None
Next
Current
None
L
X
X
X
L
L
L
H
L
H
X
X
L
X
X
X
H
H
X
X
X
X
X
X
L
L
H
X
L-H
L-H
L-H
X
Three-State
Three-State
–
Three-State
Truth Table
[1, 2, 3, 4, 5, 6, 7]
(continued)
Operation
Address
Used
CE
ZZ
ADV/LD
WE
BW
x
OE
CEN
CLK
DQ
Partial Write Cycle Description
[1, 2, 3, 8]
Function (CY7C1370C)
WE
H
BW
d
X
BW
c
X
BW
b
X
BW
a
X
Read
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQ
a
and
DQP
a
)
Write Byte b – (DQ
b
and
DQP
b
)
Write Bytes b, a
L
H
H
H
L
L
H
H
L
H
L
H
H
L
L
Write Byte c – (DQ
c
and
DQP
c
)
Write Bytes c, a
L
H
L
H
H
L
H
L
H
L
Write Bytes c, b
L
H
LL
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQ
d
and
DQP
d
)
Write Bytes d, a
L
L
H
H
H
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1372C)
WE
H
L
L
L
L
BW
b
x
H
H
L
L
BW
a
x
H
L
H
L
Read
Write – No Bytes Written
Write Byte a – (DQ
a
and
DQP
a
)
Write Byte b – (DQ
b
and
DQP
b
)
Write Both Bytes
Note:
8. Table only lists a partial listing of the byte write combinations. Any combination of BW
[a:d]
is valid. Appropriate write will be done based on which byte write is active.
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PDF描述 |
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| CY7C1372C-250BZI | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1370D-225BGC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1370D-250AXI | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1370D-250BGC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1370D-250BGI | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1372C-167AIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP T/R |
| CY7C1372C-167BGC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372C167BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372C-167BZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 18M-Bit 1M x 18 3.4ns 165-Pin FBGA 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 165-Pin FBGA |
| CY7C1372CV25-167BZC | 制造商:Cypress Semiconductor 功能描述: |
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