參數(shù)資料
型號(hào)： CY7C1372C-167AI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
中文描述： 1M X 18 ZBT SRAM, 3.4 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 14/27頁(yè)
文件大?。?/td> 704K
代理商： CY7C1372C-167AI
CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 14 of 27
TAP Timing and Test Conditions
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Output Times
t
TDOV
t
TDOX
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after clock rise
10
10
10
ns
ns
ns
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP AC Switching Characteristics
Over the Operating Range
[12, 13]
(continued)
Parameter
Description
Min.
Max.
Unit
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
50
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
Test Data-Out
TDO
t
TCYC
t
TMSH
t
TL
t
TH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
1.25V for 2.5V V
DDQ
2.5V
V
SS
ALL INPUT PULSES
1.25V
1.5 ns
1.5 ns
相關(guān)PDF資料
PDF描述
CY7C1372C-250BZI 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370D-225BGC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1370D-250AXI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1370D-250BGC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1370D-250BGI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1372C-167AIT 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP T/R
CY7C1372C-167BGC 制造商:Cypress Semiconductor 功能描述:
CY7C1372C167BZC 制造商:Cypress Semiconductor 功能描述:
CY7C1372C-167BZC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 18M-Bit 1M x 18 3.4ns 165-Pin FBGA 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 165-Pin FBGA
CY7C1372CV25-167BZC 制造商:Cypress Semiconductor 功能描述:
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