參數(shù)資料
型號(hào)： CY7C1370D-250BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
中文描述： 512K X 36 ZBT SRAM, 2.6 ns, PBGA119
封裝： (14 X 22 X 2.4) MM, PLASTIC, BGA-119
文件頁數(shù)： 9/30頁
文件大小： 344K
代理商： CY7C1370D-250BGI
PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 9 of 30
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW
. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ
s
and DQP
X
= Three-state when OE
is inactive or when the device is deselected, and DQ
= data when OE is active.
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW
X
is valid Appropriate write will be done based on which byte write is active.
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
None
None
CE
H
X
ZZ
L
L
ADV/LD
L
H
WE
X
X
BW
x
X
X
OE
X
X
CEN
CLK
L-H
L-H
DQ
Deselect Cycle
Continue Deselect Cycle
L
L
Three-State
Three-State
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
External
Next
External
Next
External
Next
None
Next
Current
None
L
X
L
X
L
X
L
X
X
X
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
X
X
H
X
H
X
L
X
L
X
X
X
X
X
X
X
L
L
H
H
X
X
L
L
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Data In (D)
Data In (D)
Three-State
Three-State
–
Three-State
相關(guān)PDF資料
PDF描述
CY7C1370D-250BZC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1370D-250BZI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-167AXC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-167AXI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1370D-250BZC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 512KX36 2.6NS 165FBGA - Bulk
CY7C1370DV25-167 制造商:Cypress Semiconductor 功能描述:
CY7C1370DV25-167AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 2.5V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1370DV25-167AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 2.5V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1370DV25-167AXI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 2.5V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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