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| 型號(hào)： | CY7C1360B-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 256K X 36 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 14/34頁(yè) |
| 文件大?。?/td> | 895K |
| 代理商： | CY7C1360B-166BGI |
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CY7C1360B
CY7C1362B
Document #: 38-05291 Rev. *C
Page 14 of 34
Truth Table
[3, 4, 5, 6, 7, 8]
Operation
Add. Used CE
1
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
CE
3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
ADSP ADSC ADV WRITE
X
L
L
X
L
X
H
L
H
L
X
X
L
X
L
X
H
L
H
L
H
L
H
H
H
H
X
H
OE CLK
X
X
X
X
X
X
L
H
X
L
H
L
H
L
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Snooze Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
H
L
L
L
L
X
L
L
L
L
L
X
X
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Three-State
Three-State
Three-State
Three-State
Three-State
Three-State
Q
Three-State
D
Q
Three-State
Q
Three-State
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Three-State
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Three-State
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Three-State
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE
1
, CE
2
, and CE
3
are available only in the TQFP package. BGA package has only 2 chip selects CE
1
and CE
2
.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
[A:D]
is valid. Appropriate write will be done based on which byte write is active.
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