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參數(shù)資料
| 型號： | CY7C1354CV25-167BZXC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture |
| 中文描述： | 9兆位（256 × 36/512K × 18）流水線的SRAM的總線延遲，TM架構(gòu) |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 353K |
| 代理商： | CY7C1354CV25-167BZXC |
PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 13 of 25
2.5V TAP AC Test Conditions
Input pulse levels
........................................ V
SS
to 2.5V
Input rise and fall time .................................................... 1 ns
Input timing reference levels ........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 2.5V ±0.125V unless otherwise noted)
[13]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Output HIGH Voltage
Test Conditions
Min.
2.0
Max.
Unit
V
I
OH
= -1.0 mA, V
DDQ
= 2.5V
I
OH
= -100 μA,V
DDQ
= 2.5V
I
OL
= 8.0 mA, V
DDQ
= 2.5V
I
OL
= 100 μA
Output HIGH Voltage
2.1
V
Output LOW Voltage
0.4
V
Output LOW Voltage
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
0.2
V
Input HIGH Voltage
1.7
V
DD
+ 0.3
0.7
V
Input LOW Voltage
-0.3
V
Input Load Current
GND < V
IN
< V
DDQ
-5
5
μA
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
CY7C1354CV25
000
01011001000100110
00000110100
1
CY7C1356CV25
000
01011001000010110 Reserved for future use.
00000110100
Allows unique identification of SRAM vendor.
1
Indicate the presence of an ID register.
Description
Reserved for version number.
Scan Register Sizes
Register Name
Bit Size
3
1
32
69
69
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
Note:
13.All voltages referenced to V
SS
(GND).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1354CV25-200AXC | 功能描述:靜態(tài)隨機存取存儲器 256Kx36 2.5V NoBL Sync PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1354CV25-200AXCT | 功能描述:IC SRAM 9MBIT 200MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:NoBL™ 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1354CV25-200BZC | 制造商:Cypress Semiconductor 功能描述:CY7C1354CV25 9 Mb (256 K x 36) 200 MHz 2.5 V Pipelined SRAM - BGA-165 制造商:Cypress Semiconductor 功能描述:CY7C1354CV25 9 Mb (256 K x 36) 200 MHz 2.5 V Pipelined SRAM - FBGA-165 |
| CY7C1354CV25-200CKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1354D-200BZC | 制造商:Cypress Semiconductor 功能描述:SYNC SRAMS - Trays 制造商:Cypress Semiconductor 功能描述:IC SRAM 9MBIT 200MHZ 165FBGA |
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