參數(shù)資料
型號(hào): CY7C1354C-200BGI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
中文描述: 256K X 36 ZBT SRAM, 3.2 ns, PBGA119
封裝: (14 X 22 X 2.4) MM, PLASTIC, BGA-119
文件頁(yè)數(shù): 14/28頁(yè)
文件大?。?/td> 467K
代理商: CY7C1354C-200BGI
CY7C1354C
CY7C1356C
Document #: 38-05538 Rev. *G
Page 14 of 28
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
69
69
Bit Size (x18)
3
1
32
69
69
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料
PDF描述
CY7C1354C-200BGXC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BGXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BZC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356C-166BZXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356C-200AXC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
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