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參數(shù)資料
| 型號： | CY7C1352B-80AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 18 Pipilined SRAm with NoBL Architecture |
| 中文描述： | 256K X 18 ZBT SRAM, 7 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY7C1352B-80AC |
CY7C1352B
PRELIMINARY
5
Burst Write Accesses
The CY7C1352B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE
1
, CE
2
, and CE
3
) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS
[1:0]
inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Cycle Description Truth Table
[
1, 2, 3, 4, 5, 6
]
Operation
Address
used
CE
CEN
ADV/
LD/
WE
BWS
x
X
CLK
Comments
Deselected
External
1
0
L
X
L-H
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations
suspended.
Begin Read
External
0
0
0
1
X
L-H
Address latched.
Begin Write
External
0
0
0
0
Valid
L-H
Address latched, data presented
two valid clocks later.
Burst READ
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of MODE.
Burst WRITE
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of MODE.
Bytes written are determined by
BWS
[1:0]
.
Interleaved Burst Sequence
First
Address
Ax+1, Ax
Second
Address
Ax+1, Ax
Third
Address
Ax+1, Ax
Fourth
Address
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Ax+1, Ax
Second
Address
Ax+1, Ax
Third
Address
Ax+1, Ax
Fourth
Address
Ax+1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Write Cycle Descriptions
[1, 2]
Function
WE
BWS
1
X
BWS
0
X
Read
Write
No bytes written
Write Byte 0
(DQ
[7:0]
and
DP
0
)
Write Byte 1
(DQ
[15:8]
and
DP
1
)
Write All Bytes
1
0
1
1
0
1
0
0
0
1
0
0
0
Notes:
1.
X=
”
Don't Care
”
, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS
= 0 signifies at least one Byte Write Select is active, BWS
x
=
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
Write is defined by WE and BWS
. See Write Cycle Description table for details.
The DQ and DP pins are controlled by the current cycle and the OE signal.
CEN=1 inserts wait states.
Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
OE assumed LOW.
2.
3.
4.
5.
6.
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