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參數(shù)資料
| 型號(hào)： | CY7C1352B-80AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 18 Pipilined SRAm with NoBL Architecture |
| 中文描述： | 256K X 18 ZBT SRAM, 7 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 189K |
| 代理商： | CY7C1352B-80AC |
PRELIMINARY
256K x18 Pipelined SRAM with NoBL Architecture
CY7C1352B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
May 26, 2000
Features
Pin compatible and functionally equivalent to ZBT
devices MCM63Z818 and MT55L256L18P
Supports 166-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write Capability
256K x 18 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
—3.5 ns (for 166-MHz device)
—3.8 ns (for 150-MHz device)
—4.0 ns (for 143-MHz device)
—4.2 ns (for 133-MHz device)
—5.0 ns (for 100-MHz device)
—7.0 ns (for 80-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100-pin TQFP package
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352B is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consec-
utive Read/Write operations with data being transferred on ev-
ery clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Read/Write transitions. The CY7C1352B is pin/func-
tionally compatible to ZBT SRAMs MCM63Z819 and
MT55L256L18P.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
[1:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
.
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
CLK
A
[17:0]
CEN
CE1
CE2
WE
[1:0]
Mode
BWS
CE
OE
O
256Kx18
MEMORY
ARRAY
C
Logic Block Diagram
DQ
[15:0]
DP
[1:0]
DD
Q
18
CE
CONTROL
and WRITE
LOGIC
3
R
a
ADV/LD
18
18
18
18
18
Selection Guide
-166
-150
-143
-133
-100
-80
Maximum Access Time (ns)
3.5
3.8
4.0
4.2
5.0
7.0
Maximum Operating Current (mA)
Commercial
400
375
350
300
250
200
Maximum CMOS Standby Current (mA) Commercial
5
5
5
5
5
5
Shaded areas contain advance information.
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參數(shù)描述 |
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| CY7C1352F-100AC | 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1352F-133AC | 功能描述:IC SRAM 4.5MBIT 133MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1352F-133ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1352F-200AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1352G-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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