參數(shù)資料
型號(hào): CY7C1352B-143AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 256K x 18 Pipilined SRAm with NoBL Architecture
中文描述: 256K X 18 ZBT SRAM, 4 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù): 9/12頁(yè)
文件大?。?/td> 189K
代理商: CY7C1352B-143AC
CY7C1352B
PRELIMINARY
9
Switching Waveforms
CEN
CLK
ADDRESS
CE
WE &
BWS
[1:0]
1a
Data-
In/Out
t
CYC
t
CH
t
CL
RA1
t
AH
t
AS
t
WS
t
WH
t
CES
t
CEH
t
CO
Q4
Out
= DON
T CARE
= UNDEFINED
The combination of WE & BWS
[1:0]
defines a write cycle (see Write Cycle Description table).
CE is the combination of CE
1
, CE
2
, and CE
3
. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
OE held LOW.
D5
In
R
W
D
W
R
R
R
S
R
D
D
WA2
RA3
RA4
WA5
RA6
RA7
t
CLZ
t
DOH
1a
t
CHZ
Device
originally
deselected
Q7
Out
t
CHZ
t
CENS
t
CENH
t
DOH
Read/Write/Deselect Sequence
CEN HIGH blocks
all synchronous inputs
Q6
Out
t
DS
t
DH
Q1
Out
Q3
Out
D2
In
相關(guān)PDF資料
PDF描述
CY7C1352B-150AC 256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-166AC 256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-80AC 256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1353F 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-100AC 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
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