參數(shù)資料
型號: CY7C1352B-143AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 256K x 18 Pipilined SRAm with NoBL Architecture
中文描述: 256K X 18 ZBT SRAM, 4 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù): 6/12頁
文件大小: 189K
代理商: CY7C1352B-143AC
CY7C1352B
PRELIMINARY
6
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................
65
°
C to +150
°
C
Ambient Temperature with
Power Applied
..................................................
55
°
C to +125
°
C
Supply Voltage on V
DD
Relative to GND
.........
0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[7]
.....................................
0.5V to V
DDQ
+ 0.5V
DC Input Voltage
[7]
..................................
0.5V to V
DDQ
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[8]
0
°
C to +70
°
C
V
DD
/V
DDQ
3.3V ± 5%
Com
l
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
DD
V
DDQ
V
OH
V
OL
V
IH
V
IL
I
X
Power Supply Voltage
3.135
3.465
V
I/O Supply Voltage
3.135
3.465
V
Output HIGH Voltage
V
DD
= Min., I
OH
=
4.0 mA
[9]
V
DD
= Min., I
OL
= 8.0 mA
[9]
2.4
V
Output LOW Voltage
0.4
V
Input HIGH Voltage
Input LOW Voltage
[7]
2.0
0.3
5
30
5
V
DD
+
0.3V
0.8
V
V
μ
A
μ
A
μ
A
mA
Input Load Current
GND
V
I
V
DDQ
5
Input Current of MODE
Output Leakage Current GND
V
I
V
DDQ,
Output Disabled
V
DD
Operating Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
30
I
OZ
I
CC
5
5.0-ns cycle, 166 MHz
400
6.6-ns cycle, 150 MHz
375
mA
7.0-ns cycle, 143 MHz
350
mA
7.5-ns cycle, 133 MHz
300
mA
10-ns cycle, 100 MHz
250
mA
12.5-ns cycle, 80 MHz
200
mA
I
SB1
Automatic CE
Power-Down
Current
TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
f = f
MAX
= 1/t
CYC
5.0-ns cycle, 166 MHz
90
mA
6.6-ns cycle, 150 MHz
80
mA
7.0-ns cycle, 143 MHz
70
mA
7.5-ns cycle, 133 MHz
60
mA
10-ns cycle, 100 MHz
50
mA
12.5-ns cycle, 80 MHz
40
mA
I
SB2
Automatic CE Power-
Down Current
CMOS
Inputs
Max. V
DD
, Device Deselected, V
IN
0.3V or V
IN
> V
DDQ
0.3V,
f = 0
All speed grades
5
mA
I
SB3
Automatic CE Power-
Down Current
CMOS
Inputs
Max. V
DD
, Device Deselected, or
V
IN
0.3V or V
IN
> V
DDQ
0.3V
f = f
MAX
= 1/t
CYC
5.0-ns cycle, 166 MHz
80
mA
6.6-ns cycle, 150 MHz
70
mA
7.0-ns cycle, 143 MHz
60
mA
7.5-ns cycle, 133 MHz
50
mA
10-ns cycle, 100 MHz
40
mA
12.5-ns cycle, 80 MHz
30
mA
Shaded areas contain advance information.
Notes:
7.
8.
9.
Minimum voltage equals
2.0V for pulse duration less than 20 ns.
T
is the case temperature.
The load used for V
OH
and V
CL
testing is shown in part (b) of A/C Test Loads and Waveforms.
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