- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298975 > CY7C1339B-133BGIT (CYPRESS SEMICONDUCTOR CORP) 128K X 32 CACHE SRAM, 4 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號： | CY7C1339B-133BGIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 32 CACHE SRAM, 4 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 527K |
| 代理商： | CY7C1339B-133BGIT |
CY7C1339B
Document #: 38-05141 Rev. *A
Page 10 of 17
Switching Characteristics Over the Operating Range[10, 12, 13]
Parameter
Description
-166
-133
-100
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tCYC
Clock Cycle Time
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
1.9
3.5
ns
tCL
Clock LOW
1.7
1.9
3.5
ns
tAS
Address Set-Up Before CLK Rise
1.5
ns
tAH
Address Hold After CLK Rise
0.5
ns
tCO
Data Output Valid After CLK Rise
3.5
4.0
5.5
ns
tDOH
Data Output Hold After CLK Rise
1.5
2.0
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
2.0
2.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
ns
tWES
BWE, GW, BW[3:0] Set-up Before CLK Rise
2.0
2.5
ns
tWEH
BWE, GW, BW[3:0] Hold After CLK Rise
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
2.0
2.5
ns
tADVH
ADV Hold After CLK Rise
0.5
ns
tDS
Data Input Set-up Before CLK Rise
1.5
ns
tDH
Data Input Hold After CLK Rise
0.5
ns
tCES
Chip Select Set-up
2.0
2.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
ns
tCHZ
Clock to High-Z[12]
3.5
ns
tCLZ
Clock to Low-Z[12]
0
ns
tEOHZ
OE HIGH to Output High-Z[12, 13]
3.5
5.5
ns
tEOLZ
OE LOW to Output Low-Z[12, 13]
0
ns
tEOV
OE LOW to Output Valid[12]
3.5
4.0
5.5
ns
Notes:
11.
Unless otherwise noted, test conditions assume signal transition time of 3.0/2.5 ns or less, timing reference levels of 1.5/1.25V, input pulse levels of 0 to
3.0/2.5V for 3.3/2.5V VDDQ respectively, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (c) of AC test loads diagram.
12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mv from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1339G-200AXCT | 128K X 32 CACHE SRAM, 2.8 ns, PQFP100 |
| CY7C1347D-250BGC | 128K X 36 CACHE SRAM, 2.4 ns, PBGA119 |
| CY7C1512JV18-267BZXC | 4M X 18 QDR SRAM, 0.45 ns, PBGA165 |
| CY7C1515AV18-250BZXI | 2M X 36 QDR SRAM, 0.45 ns, PBGA165 |
| CY7C1522JV18-250BZI | 8M X 8 DDR SRAM, 0.45 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1339F-100AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4M-Bit 128K x 32 4.5ns 100-Pin TQFP |
| CY7C1339F-100BGI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1339F-100BGIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4M-Bit 128K x 32 4.5ns 119-Pin BGA T/R |
| CY7C1339F-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4M-Bit 128K x 32 4ns 100-Pin TQFP |
| CY7C1339F-166AC | 制造商:Rochester Electronics LLC 功能描述:128KX32 3.3V SYNC-PL SRAM (2.5/3.3V I/O) 1CD - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。