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參數(shù)資料
| 型號： | CY7C1320BV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM) |
| 中文描述： | 18兆位的DDR - II SRAM的2字突發(fā)架構(gòu)（2字突發(fā)結(jié)構(gòu),18 -兆位的DDR - II SRAM的） |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 469K |
| 代理商： | CY7C1320BV18 |
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CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Document Number: 38-05621 Rev. *C
Page 9 of 28
Application Example
[1]
Notes:
1. The above application shows two DDR-II used.
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. On CY7C1318BV18 and CY7C1320BV18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1316BV18, “A1” represents A + ‘0’ and A2 represents A + ‘1’.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle; read data on
consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
L-H
L
L
D(A1) at K(t + 1)
↑
D(A2) at K(t + 1)
↑
L-H
L
H
Q(A1) at C(t + 1)
↑
Q(A2) at C(t + 2)
↑
L-H
H
X
X
X
High-Z
Previous State
High-Z
Previous State
Stopped
Burst Address Table
(CY7C1318BV18, CY7C1320BV18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
LD#
Vterm = 0.75V
Vterm = 0.75V
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
LD#
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
BUS
MASTER
(CPU
or
ASIC)
SRAM#1
SRAM#2
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
R = 50
ohms
R = 250
ohms
R
= 250ohms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1316BV18 | 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM) |
| CY7C1318BV18 | 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM) |
| CY7C192 | 64K x 4 Static RAM with Separate I/O(帶獨立的輸入/輸出口的64K x 4靜態(tài) RAM) |
| CY7C194B | 256 Kb (64K x 4) Static RAM |
| CY7C194B-15PC | 256 Kb (64K x 4) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1320BV18-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1320BV18-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1320BV18-167BZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1320BV18200BZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin FBGA |
| CY7C1320BV18-200BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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