參數(shù)資料
型號: CY7C1250V18-300BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述: 1M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 23/27頁
文件大?。?/td> 1037K
代理商: CY7C1250V18-300BZXI
CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Document Number: 001-06348 Rev. *C
Page 23 of 27
Switching Waveforms
Read/Write/Deselect Sequence
[27, 28, 29]
Figure 5. Waveform for 2.0 Cycle Read Latency
DON’T CARE
UNDEFINED
1
2
3
4
5
6
7
8
9
10
READ
READ
READ
NOP
WRITE
WRITE
t
NOP
11
K
K
LD
R/W
A
tKH
tKL
tCYC
tHC
tSA
tHA
SC
A0
A1
A2
A3
A4
CQ
CQ
QVLD
QVLD
t
NOP
t
QVLD
t
tCCQO
tCQOH
t
tCQOH
QVLD
t
NOP
DQ
KHKH
12
(Read Latency = 2.0 Cycles)
NOP
NOP
CCQO
tSD
HD
tSD
tHD
tCLZ
tCHZ
D20
D21
D30
D31
t
CQDOH
Q00
Q11
Q01
Q10
tDOH
tCO
Q40
Q41
tCQD
t
t
tCQH
CQHCQH
Notes
27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
28.Outputs are disabled (High-Z) one clock cycle after a NOP.
29.The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency
operation, it may be required to avoid bus contention.
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相關PDF資料
PDF描述
CY7C1250V18-333BZC 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1250V18-333BZI 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1250V18-333BZXC 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1250V18-333BZXI 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1250V18-375BZC 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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