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參數(shù)資料
| 型號： | CY7C1250V18-300BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 1M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 1037K |
| 代理商： | CY7C1250V18-300BZXI |
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Document Number: 001-06348 Rev. *C
Page 11 of 27
Write Cycle Descriptions
The write cycle descriptions table for CY7C1250V18 follows.
[2, 8]
BWS
0
BWS
1
BWS
2
BWS
3
K
K
Comments
L
L
L
L
L-H
–
During the data portion of a write sequence, all four bytes (D
[35:0]
) are written
into the device.
L
L
L
L
–
L-H
During the data portion of a write sequence, all four bytes (D
[35:0]
) are written
into the device.
L
H
H
H
L-H
–
During the data portion of a write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
remains unaltered.
L
H
H
H
–
L-H
During the data portion of a write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
remains unaltered.
H
L
H
H
L-H
–
During the data portion of a write sequence, only the byte (D
[17:9]
) is written
into the device. D
[8:0]
and D
[35:18]
remain unaltered.
H
L
H
H
–
L-H
During the data portion of a write sequence, only the byte (D
[17:9]
) is written
into the device. D
[8:0]
and D
[35:18]
remain unaltered.
H
H
L
H
L-H
–
During the data portion of a write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
remain unaltered.
H
H
L
H
–
L-H
During the data portion of a write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
remain unaltered.
H
H
H
L
L-H
–
During the data portion of a write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
remains unaltered.
H
H
H
L
–
L-H
During the data portion of a write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
remains unaltered.
H
H
H
H
L-H
–
No data is written into the device during this portion of a write operation.
H
H
H
H
–
L-H
No data is written into the device during this portion of a write operation.
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| CY7C1250V18-333BZC | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1250V18-333BZI | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1250V18-333BZXC | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1250V18-333BZXI | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1250V18-333BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 36M Q2+ B2 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1250V18-333BZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1250V18-333BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 36-Mbit DDR-II+ 靜態(tài)隨機(jī)存取存儲器 1.8volts RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1250XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1262XV18-366BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 36MB (2Mx18) 1.8v 366MHz QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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