參數(shù)資料
型號(hào): CY7C1241V18
廠商: Cypress Semiconductor Corp.
英文描述: 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述: 36兆位的國(guó)防評(píng)估報(bào)告⑩- II SRAM的4字突發(fā)架構(gòu)(2.0周期讀寫延遲)
文件頁(yè)數(shù): 16/28頁(yè)
文件大?。?/td> 1042K
代理商: CY7C1241V18
CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Document Number: 001-06365 Rev. *C
Page 16 of 28
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range
[12, 13, 14]
Parameter
Description
Test Conditions
I
OH
=
2.0 mA
I
OH
=
100
μ
A
I
OL
= 2.0 mA
I
OL
= 100
μ
A
Min
Max
Unit
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Output HIGH Voltage
1.4
V
Output HIGH Voltage
1.6
V
Output LOW Voltage
0.4
V
Output LOW Voltage
0.2
V
Input HIGH Voltage
0.65V
DD
–0.3
V
DD
+ 0.3
0.35V
DD
5
V
Input LOW Voltage
V
μ
A
Input and Output Load Current
GND
V
I
V
DD
–5
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
108
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Notes
12.These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in
“Electrical Characteristics” on page 21
.
13.Overshoot: V
(AC) < V
+ 0.3V (pulse width less than t
CYC
/2). Undershoot: V
IL
(AC) >
0.3V (pulse width less than t
CYC
/2).
14.All voltage refers to Ground.
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1241V18-300BZC 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1241V18-300BZI 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1241V18-300BZXC 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1241V18-300BZXI 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1243V18 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
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