參數(shù)資料
型號: CY7C1241V18
廠商: Cypress Semiconductor Corp.
英文描述: 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述: 36兆位的國防評估報告⑩- II SRAM的4字突發(fā)架構(gòu)(2.0周期讀寫延遲)
文件頁數(shù): 12/28頁
文件大?。?/td> 1042K
代理商: CY7C1241V18
CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Document Number: 001-06365 Rev. *C
Page 12 of 28
Write Cycle Descriptions
The write cycle description table for CY7C1245V18 follows.
[2, 10]
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
Comments
L–H
During the data portion of a write sequence, all four bytes (D
[35:0]
) are written
into the device.
L–H During the data portion of a write sequence, all four bytes (D
[35:0]
) are written
into the device.
During the data portion of a write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[17:9]
) is written
into the device. D
[8:0]
and D
[35:18]
remain unaltered.
L–H During the data portion of a write sequence, only the byte (D
[17:9]
) is written
into the device. D
[8:0]
and D
[35:18]
remain unaltered.
During the data portion of a write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
remain unaltered.
L–H During the data portion of a write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
remain unaltered.
During the data portion of a write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
remains unaltered.
L–H During the data portion of a write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
remains unaltered.
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
L
L
L
L
L
H
H
H
L–H
L
H
H
H
H
L
H
H
L–H
H
L
H
H
H
H
L
H
L–H
H
H
L
H
H
H
H
L
L–H
H
H
H
L
H
H
H
H
H
H
H
H
L–H
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CY7C1241V18-300BZC 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
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