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參數(shù)資料
| 型號： | CY7C1241V18-300BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | CY7C1241V18-300BZXI |
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CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Document Number: 001-06365 Rev. *C
Page 12 of 28
Write Cycle Descriptions
The write cycle description table for CY7C1245V18 follows.
[2, 10]
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
Comments
L–H
–
During the data portion of a write sequence, all four bytes (D
[35:0]
) are written
into the device.
L–H During the data portion of a write sequence, all four bytes (D
[35:0]
) are written
into the device.
–
During the data portion of a write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
remains unaltered.
–
During the data portion of a write sequence, only the byte (D
[17:9]
) is written
into the device. D
[8:0]
and D
[35:18]
remain unaltered.
L–H During the data portion of a write sequence, only the byte (D
[17:9]
) is written
into the device. D
[8:0]
and D
[35:18]
remain unaltered.
–
During the data portion of a write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
remain unaltered.
L–H During the data portion of a write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
remain unaltered.
–
During the data portion of a write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
remains unaltered.
L–H During the data portion of a write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
H
H
H
H
L–H
–
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相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1243V18 | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1243V18-300BZC | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1243V18-300BZXC | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1243V18-300BZXI | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1245V18 | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1243KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 36MB (2Mx18) 1.8v 400MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1243KV18-450BZC | 功能描述:靜態(tài)隨機存取存儲器 36MB (2Mx18) 1.8v 450MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C12451KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mb x 36 400 MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C12451KV18-400BZXC | 功能描述:靜態(tài)隨機存取存儲器 1M X 36 400MHz QDR II+ 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1245KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 36MB (1Mx36) 1.8v 400MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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