參數(shù)資料
型號(hào)： CY7C1176V18-333BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述： 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
文件頁(yè)數(shù)： 27/29頁(yè)
文件大?。?/td> 956K
代理商： CY7C1176V18-333BZC
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 27 of 29
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CY7C1161V18-333BZI
CY7C1176V18-333BZI
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CY7C1165V18-333BZI
CY7C1161V18-333BZXI
CY7C1176V18-333BZXI
CY7C1163V18-333BZXI
CY7C1165V18-333BZXI
CY7C1161V18-300BZC
CY7C1176V18-300BZC
CY7C1163V18-300BZC
CY7C1165V18-300BZC
CY7C1161V18-300BZXC
CY7C1176V18-300BZXC
CY7C1163V18-300BZXC
CY7C1165V18-300BZXC
CY7C1161V18-300BZI
CY7C1176V18-300BZI
CY7C1163V18-300BZI
CY7C1165V18-300BZI
CY7C1161V18-300BZXI
CY7C1176V18-300BZXI
CY7C1163V18-300BZXI
CY7C1165V18-300BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
300
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Ordering Information
(continued)
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit
www.cypress.com
for actual products offered.
Speed
(MHz)
Ordering Code
Package
Diagram
Package Type
Operating
Range
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1176V18-333BZI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-300BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1214F-100AC 制造商:Cypress Semiconductor 功能描述:
CY7C1214F-100ACT 制造商:Cypress Semiconductor 功能描述:
CY7C1215F-166AC 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述:
CY7C1215H-166AXC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk
CY7C1217H-133AXC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk
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