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參數(shù)資料
| 型號： | CY7C1176V18-300BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大小： | 956K |
| 代理商： | CY7C1176V18-300BZXC |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 20 of 29
Power Up Sequence in QDR-II+ SRA
During power up, when the DOFF is tied HIGH, the DLL gets
locked after 2048 cycles of stable clock. .QDR-II+ SRAMs must
be powered up and initialized in a predefined manner to prevent
undefined operations.
Power Up Sequence
■
Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
— Apply V
DD
before V
DDQ
— Apply V
DDQ
before V
REF
or at the same time as V
REF
■
Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL
DLL Constraints
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
KC Var
■
The DLL functions at frequencies down to 120 MHz
■
If the input clock is unstable and the DLL is enabled, then the
DLL locks onto an incorrect frequency, causing unstable SRAM
behavior. To avoid this, provide 2048 cycles stable clock to
relock to the desired clock frequency
Power Up Waveforms
Figure 4. Power Up Waveforms
K
K
Fix HIGH (tie to VDDQ)
VDD/VDDQ
DOFF
Clock Start (Clock Starts after VDD/VDDQ is Stable)
Unstable Clock
> 2048 Stable Clock
Start Normal
Operation
~
~
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1176V18-300BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215F-166AC | 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
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