參數(shù)資料
型號(hào): CY7C1176V18-300BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165
文件頁數(shù): 15/29頁
文件大小: 956K
代理商: CY7C1176V18-300BZXC
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 15 of 29
TAP Controller State Diagram
Figure 2. Tap Controller State Diagram
[12]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
Note
12.The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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相關(guān)PDF資料
PDF描述
CY7C1176V18-300BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
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