參數(shù)資料
型號(hào): CY7C1176V18-300BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165
文件頁(yè)數(shù): 2/29頁(yè)
文件大小: 956K
代理商: CY7C1176V18-300BZXC
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 2 of 29
Logic Block Diagram (CY7C1161V18)
Logic Block Diagram (CY7C1176V18)
5
CLK
Gen.
A
(18:0)
K
K
Control
Logic
Address
Register
D
[7:0]
R
Read Data Reg.
RPS
WPS
NWS
[1:0]
Q
[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
19
8
32
8
V
REF
W
Write
Reg
16
A
(18:0)
19
5
5
5
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
QVLD
5
CLK
Gen.
A
(18:0)
K
K
Control
Logic
Address
Register
D
[8:0]
R
Read Data Reg.
RPS
WPS
BWS
[0]
Q
[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
9
36
9
V
REF
W
Write
Reg
18
A
(18:0)
19
5
5
5
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF
QVLD
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相關(guān)PDF資料
PDF描述
CY7C1176V18-300BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
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