參數(shù)資料
型號: CY7C1148V18
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述: 18兆位的DDR - II SRAM的2字突發(fā)架構(gòu)(2.0周期讀寫延遲)
文件頁數(shù): 19/27頁
文件大?。?/td> 969K
代理商: CY7C1148V18
CY7C1146V18
CY7C1157V18
CY7C1148V18
CY7C1150V18
Document Number: 001-06621 Rev. *C
Page 19 of 27
Power Up Sequence in DDR-II+ SRAM
During Power Up, when the DOFF is tied HIGH, the DLL gets
locked after 2048 cycles of stable clock. DDR-II+ SRAMs must
be powered up and initialized in a predefined manner to prevent
undefined operations.
Power Up Sequence
Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
Apply V
DD
before V
DDQ
Apply V
DDQ
before V
REF
or at the same time as V
REF
Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
DLL Constraints
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
KC Var
.
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
Power Up Waveforms
Figure 5. Power Up Waveforms
K
K
Fix HIGH (tie to VDDQ)
VDD/VDDQ
DOFF
Clock Start (Clock Starts after VDD/VDDQ is Stable)
Unstable Clock
> 2048 Stable Clock
Start Normal
Operation
~
~
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1148V18-333BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1148V18-333BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1148V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1148V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1148V18-375BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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