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參數(shù)資料
| 型號： | CY7C1032-8JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64K x 18 Synchronous Cache RAM |
| 中文描述： | 64K X 18 CACHE SRAM, 8.5 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 282K |
| 代理商： | CY7C1032-8JC |
CY7C1031
CY7C1032
Document #: 38-05278 Rev. *A
Page 6 of 13
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[9]
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CDV
t
DOH
t
ADS
t
ADSH
t
WES
t
WEH
t
ADVS
t
ADVH
t
DS
t
DH
t
CSS
t
CSH
t
CSOZ
t
EOZ
t
EOV
t
WEOZ
t
WEOV
Notes:
8. Resistor values for V
= 5V are: R1 = 1179
and R2 = 868
. Resistor values for V
= 3.3V are R1 = 317
and R2 = 348
.
9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
/I
and load capacitance. Shown in (a) and (b) of AC Test Loads.
10.Do not use the burst mode, if device operates at a frequency above 50 MHz.
11. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
12.At any given voltage and temperature, t
WEOZ
min. is less than t
WEOV
min.
Description
7C1031-8
7C1032-8
Min.
15
[10]
5
5
2.5
0.5
7C1031-10
7C1032-10
Min.
20
8
8
2.5
0.5
7C1031-12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
Max.
Min.
20
8
8
2.5
0.5
Max.
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
WH, WL Set-Up Before CLK Rise
WH, WL Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-Up
Chip Select Hold After CLK Rise
Chip Select Sampled to Output High Z
[11]
OE HIGH to Output High Z
[11]
OE LOW to Output Valid
WH or WL Sampled LOW to Output High Z
[11, 12]
WH or WL Sampled HIGH to Output Valid
[12]
8.5
10
12
3
3
3
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2
2
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2
2
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2
2
6
6
5
5
6
6
5
6
10
7
7
6
7
12
8.5
3.0V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
OUTPUT
R1
R2
5 pF
INCLUDING
JIGAND
SCOPE
(a)
(b)
ALL INPUT PULSES
OUTPUT
R
L
= 50
Z
0
= 50
V
L
=1.5V
V
CCQ
[8]
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