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參數(shù)資料
| 型號(hào)： | CY7C1032-8JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64K x 18 Synchronous Cache RAM |
| 中文描述： | 64K X 18 CACHE SRAM, 8.5 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 282K |
| 代理商： | CY7C1032-8JC |
CY7C1031
CY7C1032
Document #: 38-05278 Rev. *A
Page 4 of 13
Pin Descriptions
Signal Name
Input Signals
CLK
I/O
Description
I
Clock signal
. It is used to capture the address, the data to be written, and the following control
signals: ADSP, ADSC, CS, WH, WL, and ADV. It is also used to advance the on-chip
auto-address-increment logic (when the appropriate control signals have been set).
Sixteen address lines used to select one of 64K locations
. They are captured in an on-chip
register on the rising edge of CLK if ADSP or ADSC is LOW. The rising edge of the clock also loads
the lower two address lines, A
1
–A
0
, into the on-chip auto-address-increment logic if ADSP or ADSC
is LOW.
Address strobe from processor
. This signal is sampled at the rising edge of CLK. When this input
and/or ADSC is asserted, A
0
–A
15
will be captured in the on-chip address register. It also allows the
lower two address bits to be loaded into the on-chip auto-address-increment logic. If both ADSP
and ADSC are asserted at the rising edge of CLK, only ADSP will be recognized. The ADSP input
should be connected to the ADS output of the processor. ADSP is ignored when CS is HIGH.
Address strobe from cache controller
. This signal is sampled at the rising edge of CLK. When
this input and/or ADSP is asserted, A
0
–A
15
will be captured in the on-chip address register. It also
allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. The
ADSC input should
not
be connected to the ADS output of the processor.
Write signal for the high-order half of the RAM array
. This signal is sampled by the rising edge
of CLK. If WH is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of
DQ
15
–DQ
8
and DP
1
from the on-chip data register into the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write
signal, WH, is ignored. Note that ADSP has no effect on WH if CS is HIGH.
Write signal for the low-order half of the RAM array
. This signal is sampled by the rising edge
of CLK. If WL is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of
DQ
7
–DQ
0
and DP
0
from the on-chip data register into the selected RAM location. There is one
exception to this. If ADSP, WL, and CS are asserted (LOW) at the rising edge of CLK, the write
signal, WL, is ignored. Note that ADSP has no effect on WL if CS is HIGH.
Advance
. This signal is sampled by the rising edge of CLK. When it is asserted, it automatically
increments the 2-bit on-chip auto-address-increment counter. In the CY7C1032, the address will
be incremented linearly. In the CY7C1031, the address will be incremented according to the
Pentium/486 burst sequence. This signal is ignored if ADSP or ADSC is asserted concurrently with
CS. Note that ADSP has no effect on ADV if CS is HIGH.
Chip select
. This signal is sampled by the rising edge of CLK. If CS is HIGH and ADSC is LOW,
the SRAM is deselected. If CS is LOW and ADSC or ADSP is LOW, a new address is captured by
the address register. If CS is HIGH, ADSP is ignored.
Output enable
. This signal is an asynchronous input that controls the direction of the data I/O pins.
If OE is asserted (LOW), the data pins are outputs, and the SRAM can be read (as long as CS was
asserted when it was sampled at the beginning of the cycle). If OE is deasserted (HIGH), the data
I/O pins will be three-stated, functioning as inputs, and the SRAM can be written.
A
15
–A
0
I
ADSP
I
ADSC
I
WH
I
WL
I
ADV
I
CS
I
OE
I
Bidirectional Signals
DQ
15
–DQ
0
I/O
Sixteen bidirectional data I/O lines
. DQ
15
–DQ
8
are inputs to and outputs from the high-order half
of the RAM array, while DQ
7
–DQ
0
are inputs to and outputs from the low-order half of the RAM
array. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK.
As outputs, they carry the data read from the selected location in the RAM array. The direction of
the data pins is controlled by OE: when OE is HIGH, the data pins are three-stated and can be used
as inputs; when OE is LOW, the data pins are driven by the output buffers and are outputs.
DQ
15
–DQ
8
and DQ
7
–DQ
0
are also three-stated when WH and WL, respectively, is sampled LOW
at clock rise.
Two bidirectional data I/O lines
. These operate in exactly the same manner as DQ
15
–DQ
0
, but
are named differently because their primary purpose is to store parity bits, while the DQs’ primary
purpose is to store ordinary data bits. DP
1
is an input to and an output from the high-order half of
the RAM array, while DP
0
is an input to and an output from the lower-order half of the RAM array.
DP
1
–DP
0
I/O
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