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參數(shù)資料
| 型號(hào)： | CY7C1031-8NC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 18 CACHE SRAM, 8.5 ns, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 343K |
| 代理商： | CY7C1031-8NC |
PRELIMINARY
64K x 18 Synchronous
Cache RAM
CY7C1031
CY7C1032
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 1993 – Revised March 1995
1CY 7C10 32
Features
Supports 66-MHz Pentium microprocessor cache
systems with zero wait states
64K by 18 common I/O
Fast clock-to-output times
— 8.5 ns
Two-bit wraparound counter supporting Pentium mi-
croprocessor and 486 burst sequence (7C1031)
Two-bit wraparound counter supporting linear burst se-
quence (7C1032)
Separate processor and controller address strobes
Synchronous self-timed write
Direct interface with the processor and external cache
controller
Asynchronous output enable
I/Os capable of 3.3V operation
JEDEC-standard pinout
52-pin PLCC and PQFP packaging
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
The CY7C1031 is designed for Intel Pentium and i486
CPU-based systems; its counter follows the burst sequence of
the Pentium and the i486 processors. The CY7C1032 is archi-
tected for processors with linear burst sequences. Burst ac-
cesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address advance-
ment (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip select input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
Pin Configuration
1031–1
Top View
PLCC
1031–2
18
16
14
2
16
99
18
CLK
TIMING
CONTROL
ADDR
REG
ADV
LOGIC
REGISTER
64K X 9
RAM ARRAY
64K X 9
RAM ARRAY
OE
1
7C1031
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 65432
52 51 50 49 48 47
DQ8
DQ9
VCCQ
VSSQ
DQ10
DQ11
DQ12
DQ13
VSSQ
VCCQ
DQ14
DQ15
DP1
7C1032
DP0
DQ7
DQ6
VCCQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VCCQ
DQ1
DQ0
A15 –A0
DATA IN
ADSP
ADSC
WH
WL
WH
WL
DQ15 –DQ0
DP1 –DP0
ADV
CS
[1]
Selection Guide
7C1031–7
7C1032–7
7C1031–8
7C1032–8
7C1031–10
7C1032–10
7C1031–12
7C1032–12
Maximum Access Time (ns)
7
8.5
10
12
Maximum Operating
Current (mA)
Commercial
300
280
230
Military
235
Shaded area contains advanced information.
Pentium is a trademark of Intel Corporation.
Note:
1.
DP0 and DP1 are functionally equivalent to DQx.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1032-10JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 10ns 52-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:1MB (64KX18) SYNCH RAM POWER PC BURST - Bulk |
| CY7C1032-10JCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 10ns 52-Pin PLCC T/R |
| CY7C1032-12JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C10328JC | 制造商:CYPRESS 功能描述:NEW |
| CY7C1032-8JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 8.5ns 52-Pin PLCC |
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