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參數(shù)資料
| 型號： | CY7C1442AV25-200BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 2M X 18 CACHE SRAM, 3.2 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 4264K |
| 代理商： | CY7C1442AV25-200BZC |
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36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-05350 Rev. *E
Revised June 21, 2006
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200 and 167 MHz
Registered inputs and outputs for pipelined operation
2.5V core power supply
2.5V/1.8V I/O powersupply
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single-cycle Chip Deselect
CY7C1440AV25, CY7C1442AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1446AV25 available in lead-free and non-lead- free
209-ball FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description[1]
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 SRAM
integrates 1M x 36/2M x 18/512K x 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The
CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
operates from a +2.5V core power supply while all outputs
may operate with a +2.5V/1.8V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.2
3.4
ns
Maximum Operating Current
435
385
335
mA
Maximum CMOS Standby Current
120
mA
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
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