參數(shù)資料
型號: CY7C1021CV33-8ZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 1-Mbit (64K x 16) Static RAM
中文描述: 64K X 16 STANDARD SRAM, 8 ns, PDSO44
封裝: LEAD FREE, TSOP2-44
文件頁數(shù): 3/13頁
文件大?。?/td> 379K
代理商: CY7C1021CV33-8ZXC
CY7C1021CV33
Document #: 38-05132 Rev. *G
Page 3 of 13
Pin Definitions
Pin Name
A
0
–A
15
SOJ, TSOP
Pin Number
1–5, 18–21,
24–27, 42–44
BGA Pin
Number
A3, A4, A5,
B3, B4, C3,
C4, D4, H2,
H3, H4, H5,
G3, G4, F3,
F4
B6, C6, C5,
D5, E5, F5,
F6, G6, B1,
C1, C2, D2,
E2, F2, F1,
G1
A6, D3, E3,
E4, G2, H1,
H6
G5
I/O Type
Input
Description
Address Inputs used to select one of the address locations.
I/O
0
–I/O
15[3]
7–10, 13–16,
29–32, 35–38
Input/Output
Bidirectional Data I/O lines
. Used as input or output lines
depending on operation.
NC
22, 23, 28
No Connect
No Connects
. Not connected to the die.
WE
17
Input/Control
Write Enable Input, active LOW
. When selected LOW, a Write is
conducted. When deselected HIGH, a Read is conducted.
Input/Control
Chip Enable Input, active LOW
. When LOW, selects the chip.
When HIGH, deselects the chip.
Input/Control
Byte Write Select Inputs, active LOW
. BHE controls I/O
16
–I/O
9
,
BLE controls I/O
8
–I/O
1
.
Input/Control
Output Enable, active LOW
. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
Ground
Ground for the device
.
Should be connected to ground of the
system.
Power Supply
Power Supply inputs to the device.
CE
6
B5
BHE, BLE
40, 39
B2, A1
OE
41
A2
V
SS
12,34
D1, E6
V
CC
11,33
D6, E1
Note:
3. I/O
1
–I/O
16
for SOJ/TSOP and I/O
0
–I/O
15
for BGA packages.
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